ADI公司的ADF5610是微波寬帶壓控振蕩器(VCO),工作頻率從3700MHz到14600MHz,單個射頻(RF)輸出.ADF5610和外接回路濾波器和外接基準(zhǔn)源一起,能實現(xiàn)分數(shù)N或整數(shù)N鎖相環(huán)(PLL)頻率合成器.帶差分頻率輸出的分頻器工作在57 MHz 到14600 MHz,而PLL電路的模擬和數(shù)字電源從3.1V到3.5V,而VCO的工作在4.75V-5,25V,電荷泵的電源可擴展到3.6V.ADF5610還集成了基頻從3650 MHz到7300 MHz的VCO,其差分輸出允許倍頻VCO頻率能進行1, 2, 4, 8, 16, 32, 64或128分頻,使得用戶可獲得低至57MHz RF輸出頻率.集成的鑒相器(PD)和delta-sigma (Δ-Σ)調(diào)制器,工作高達100MHz,其雜散電平為-100dBc.而相位噪音電平從7.3GHz的?115 dBc/Hz到14.6GHz的?109 dBc/Hz. RFOUT功率5dbm,可編程輸出功率電平,典型功耗815mW.主要用在軍用和國防,測試設(shè)備,時鐘發(fā)生器,無線基礎(chǔ)設(shè)備,衛(wèi)星和甚小孔徑終端(VSAT),微波無線電.本文介紹了ADF5610主要特性,功能框圖,PLL和VCO子系統(tǒng)框圖,以及評估板EV-ADF5610SD1Z主要特性,電路圖,材料清單和PCB設(shè)計圖.

The ADF5610 allows implementation of fractional-N or Integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference source. The wideband microwave voltage controlled oscillator (VCO) design permits frequency operation from 7300 MHz to 14600 MHz at a single radio frequency (RF) output. A series of frequency dividers with a differential frequency output allows operation from 57 MHz to 14600 MHz.Analog and digital power supplies for the PLL circuitry range from 3.1 V to 3.5 V, and the VCO supplies are between 4.75 V and 5.25 V. The charge pump supply voltage can be extended up to 3.6 V for improved frequency band overlap and extended upper frequency range.

The ADF5610 has an integrated VCO with a fundamental frequency of 3650 MHz to 7300 MHz. These frequencies are internally doubled and routed to the RFOUT pin. An additional differential output allows the doubled VCO frequency to be divided by 1, 2, 4, 8, 16, 32, 64, or 128, allowing the user to generate RF output frequencies as low as 57 MHz. A simple 3-wire serial port interface (SPI) provides control of all on-chip registers. To conserve power, this divider block can be disabled when not needed through the SPI interface. Likewise, the output power for both the single-ended output and the differential output are programmable via the VCO register settings. The ADF5610 also contains various power-down modes for the VCO circuitry and PLL circuitry.

The integrated phase detector (PD) and delta-sigma (Δ-Σ) modulator, capable of operating at up to 100 MHz, permit wide loop bandwidths and fast frequency tuning with a typical spurious level of ?100 dBc.

With phase noise levels from ?115 dBc/Hz at 7.3 GHz to ?109 dBc/Hz at 14.6 GHz, the ADF5610 is equipped to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. The low phase noise floor eliminates any contribution to modulator and mixer noise floor in transmitter applications.

The ADF5610 is a PLL with integrated VCO. The device features an innovative programmable performance technology that enables the ADF5610 to tailor current consumption and corresponding noise performance to individual applications by selecting either a low current consumption mode or a high performance mode for improved phase noise performance.

Additional features of the ADF5610 include approximately 3 dB of RFOUT gain control in 1.5 dB steps and 5 dB of control on the differential port in approximately 2.5 dB steps. Finally, the Δ-Σ modulator with exact frequency mode enables users to generate output frequencies with 0 Hz frequency error.

ADF5610主要特性:

RF output frequency range: 57 MHz to 14,600 MHz
RFOUT: 7300 MHz to 14,600 MHz
PDIV/NDIV: 57 MHz to 14,600 MHz
Fractional-N synthesizer and Integer N synthesizer modes
24-bit fractional modulus
Exact frequency mode for 0 Hz frequency error
Typical PFD spurious: Integrated rms jitter: <40 fs
Normalized inband phase noise floor FOM
High current mode: ?232 dBc/Hz (integer) and ?229 dBc/Hz (fractional)
Normal mode: ?229 dBc/Hz (integer) and ?226 dBc/Hz (fractional)
Maintains frequency lock over ?40℃ to +85℃ (lock and leave)
Low phase noise VCO
?115 dBc/Hz typical at 100 kHz (7.3 GHz)
?114 dBc/Hz typical at 100 kHz (10 GHz)
?109 dBc/Hz typical at 100 kHz (14.6 GHz)
RFOUT power: 5 dBm
Programmable divide by 1, 2, 4, 8, 16, 32, 64, or 128 output
Programmable output power level
Typical power dissipation: 815 mW
Programmable low current and power dissipation: <700 mW
Fast frequency hopping (autocalibration enabled): <40 μs
48-terminal, 7 mm×7 mm LGA package: 49 mm2

ADF5610應(yīng)用:

Military and defense
Test equipment
Clock generation
Wireless infrastructure
Satellite and very small aperture terminal (VSAT)
Microwave radio

圖1.ADF5610功能框圖

圖2.PLL和VCO子系統(tǒng)框圖

圖3.PLL和VCO子系統(tǒng)詳細框圖

圖4.簡化調(diào)諧VCO圖

評估板EV-ADF5610SD1Z

The EV-ADF5610SD1Z evaluates the performance of the ADF5610 frequency synthesizer with integrated VCO for phase-locked loops (PLLs). A photograph of the evaluation board is shown in Figure 1. The evaluation board contains the ADF5610 synthesizer with integrated voltage controlled oscillator (VCO), a low noise, single-ended, 50 MHz voltage controlled crystal oscillator (VCXO) reference, the HMC1031 Integer N PLL, a switch, a jumper, a loop filter, a USB interface, and subminiature Version A (SMA) connectors.

For easy programming of the synthesizer, download the Windows?-based software from the ADF5610 page at ftp://ADF5610_ftp:[email protected]. The file transfer program (FTP) user name and password are printed on the label inside the lid of the evaluation board box. The user manual and evaluation printed circuit board (PCB) schematic can also be found on the FTP site.

The EV-ADF5610SD1Z evaluation board requires a SDP-S controller board (see Figure 3), which is not included with the kit. The SDP-S allows software programming of the ADF5610 device through a USB interface.

Full specifications for the ADF5610 wideband microwave synthesizer are available in the ADF5610 data sheet, which must be consulted in conjunction with this user guide when working with the evaluation board.

評估板EV-ADF5610SD1Z主要特性:

Self contained board, including ADF5610 frequency synthesizer with integrated VCO, single-ended, 50 MHz VCXO, PLL jitter clean up circuit, loop filter (4 kHz), USB interface, and voltage regulators
Windows-based software allows control of synthesizer functions from a PC
Externally powered by a single 6 V supply

圖6.評估板EV-ADF5610SD1Z外形圖

圖7.評估板EV-ADF5610SD1Z電路圖(1)

圖8.評估板EV-ADF5610SD1Z電路圖(2)

圖9.評估板EV-ADF5610SD1Z電路圖(3)
評估板EV-ADF5610SD1Z材料清單:

圖10.評估板EV-ADF5610SD1Z PCB設(shè)計圖(1):絲印和金屬1,頂層

圖11.評估板EV-ADF5610SD1Z PCB設(shè)計圖(2):金屬2,地層

圖12.評估板EV-ADF5610SD1Z PCB設(shè)計圖(3):金屬3,RF和DC

圖13.評估板EV-ADF5610SD1Z PCB設(shè)計圖(4):金屬4,背面