現(xiàn)代通信系統(tǒng)要求通信距離遠(yuǎn)、通信容量大、傳輸質(zhì)量好。作為其關(guān)鍵技術(shù)之一的調(diào)
制解調(diào)技術(shù)一直是人們研究的一個(gè)重要方向。本論文主要討論和仿真了基于CPLD 的FSK、4FSK 系統(tǒng)單元設(shè)計(jì)，并對(duì)調(diào)制解調(diào)系統(tǒng)和CPLD 設(shè)計(jì)方法進(jìn)行了相關(guān)的研究。以VHDL 作 為設(shè)計(jì)的硬件描述語言，在Altera 公司的Maxplus2 開發(fā)平臺(tái)上進(jìn)行了程序設(shè)計(jì)及波形仿真。對(duì)各個(gè)模塊進(jìn)行CPLD 的建模，然后對(duì)各個(gè)模塊的設(shè)計(jì)內(nèi)容進(jìn)行了層層細(xì)化，最終達(dá)到模塊的具體軟硬件實(shí)現(xiàn)。
關(guān)鍵詞：頻率鍵控系統(tǒng)、CPLD、VHDL
Abstract: Long distance, large capability and high quality of transmission are required in modern communication system. Modulation and demodulation, which is one of the most key techniques in communication, has been always an important aspect people research. This thesis primarily focused on the modulation and demodulation system and the design technique of CPLD, and also discussed and simulated the digitalized FSK、4FSK systems based on CPLD. The author utilized VHDL to be the hardware describing language of design and has been waveform simulated on the basis of a CPLD development platform Maxplus2 developed by Altera. “TOP-TO-DOWN” is the main feature of this design. CPLD modeling has firstly been done for each module of system, then the design content divided into smaller parts layer to layer, and finally achieved both in hardware and software in details. The whole program has passed the hardware debugging on CPLD experiment exploitation board which takes EPM7128SLC84-7 to be the main chip.
KeyWords: FSK; CPLD; VHDL