IC設(shè)計(jì)技術(shù)中的IP核互連:隨著IC 設(shè)計(jì)復(fù)雜度的不斷提高，在SoC 中集成的IP 核越來越多，基于片上總線的SOC 設(shè)計(jì)技術(shù)解決了大規(guī)模集成電路的設(shè)計(jì)難點(diǎn)，但是片上總線的應(yīng)用帶來了可擴(kuò)展性差、平均通信效率低等問題。近幾年來，將英特網(wǎng)絡(luò)中分層互連的思想引入到SOC 設(shè)計(jì)中IP 核的互連上來，提出了全新的集成電路體系結(jié)構(gòu)片上網(wǎng)絡(luò)（NOC），NOC 從多處理體系結(jié)構(gòu)、消除時(shí)鐘樹以節(jié)省資源、實(shí)現(xiàn)并行通信等幾個(gè)方面，展示了優(yōu)于總線結(jié)構(gòu)的本質(zhì)和特性，成功地解決了SOC 設(shè)計(jì)中存在的問題。
關(guān)鍵詞：集成電路；IP；片上系統(tǒng)；片上總線；片上網(wǎng)絡(luò)

Abstract：With the improvement of complexity in IC design,IP reuse has become one of
the main solution in SOC design. SOC design technology based on bus has some
disadvantages,such as poor scalability and lower communication efficiency,etc. In recent
years, a new architecture NOC is proposed, in which bus interconnection for chip is replaced
by computer network interconncetion. And it will overcome the disadvantages of SOC design
thoroughly and become a mainstream design technology for the next generation intergrated
circuit.
Key Words：IC；IP；SOC；Bus on chip； Network on chip