系統級ESD：一盎司的預防勝過一磅重的治療

　　這些天來，我有更多的客戶互動像我最近做的。這似乎是一個有點瘋狂的工程師為我們的團隊在Semtech公司解決了他的系統級ESD問題的一些第十一小時的幫助。這個家伙被一些煩人的ESD尖峰伏擊了。不僅他的產品沒有遵守，但他甚至看到ESD誘導失敗的一些早期田間試驗。更糟糕的是，他很快就沒時間解決這些問題了。他的管理變得越來越不耐煩，并增加壓力，有一個大的，苛刻的最終客戶等待這個產品。該計劃不能容忍另一個延遲，情況越來越嚴重，當他向我們伸出手來。

　　當我們與工程師更多地了解這個問題的挑戰和性質時，很明顯，有一些簡單的東西，如果應用在設計周期的前端，可以幫助創建一個“軟著陸”解決問題。

　　First off， our friend had not implemented protection clamps at any of the I/O interfaces of the product. At a minimum， it would have been wise to layout the PCB pads for TVS clamps as a “safety valve” move should he need protection. Even if he did not populate those pads with ESD clamp devices， at least he would have allowed for the option to later do so. However， what really made this product an EMC challenge was the high-speed performance silicon driving the I/O. While the latest （65 nm， 45 nm and 28 nm） high-speed communication ICs offer incredible speed and power saving performance， they also tend to be more susceptible to latch-up or damage from fast rise-time ESD transients. As it was， even a weaker/lower threshold ESD zap could send his board out of commission.