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電子發燒友網>電子資料下載>電源技術>精密模擬前端帶有雙斜率轉換器TC500/A/510/514數據表

精密模擬前端帶有雙斜率轉換器TC500/A/510/514數據表

2017-10-11 | rar | 0.55 MB | 次下載 | 免費

資料介紹

  TheTC500/A/510/514 family are precision analog front ends that implement dual slope A/D converters having a maximum resolution of 17 bits plus sign. As a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. The TC500 is the base (16-bit max) device and requires both positive and negative power supplies. The TC500A is identical to the TC500 with the exception that it has improved linearity, allowing it to operate to a maximum resolution of 17 bits. The TC510 adds an onboard negative power supply converter for singlesupply operation. The TC514 adds both a negative power supply converter and a 4-input differential analog multiplexer. Each device has the same processor control interface consisting of 3 wires: control inputs (A and B) and zerocrossing comparator output (CMPTR)。 The processor manipulates A, B to sequence the TC5XX through four phases of conversion: auto-zero, integrate, deintegrate and integrator zero. During the auto-zero phase, offset voltages in the TC5XX are corrected by a closed loop feedback mechanism. The input voltage is applied to the integrator during the integrate phase. This causes an integrator output dv/dt directly proportional to the magnitude of the input voltage. The higher the input voltage, the greater the magnitude of the voltage stored on the integrator during this phase. At the start of the de-integrate phase, an external voltage reference is applied to the integrator and, at the same time, the external host processor starts its onboard timer. The processor maintains this state until a transition occurs on the CMPTR output, at which time the processor halts its timer. The resulting timer count is the converted analog data. Integrator zero (the final phase of conversion) removes any residue remaining in the integrator in preparation for the next conversion. The TC500/A/510/514 offer high resolution (up to 17 bits), superior 50/60 Hz noise rejection, low-power operation, minimum I/O connections, low input bias currents and lower cost compared to other converter technologies having similar conversion speeds.
精密模擬前端帶有雙斜率轉換器TC500/A/510/514數據表

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