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用于中間總線結(jié)構(gòu)的高降壓比降壓轉(zhuǎn)換器

2453872 2017-06-21 | rar | 0.15 MB | 次下載 | 免費(fèi)

資料介紹

　　使用分布式電源架構(gòu)的電信系統(tǒng)和數(shù)據(jù)中心計(jì)算機(jī)通常使用中間總線電壓來(lái)驅(qū)動(dòng)遍布系統(tǒng)板的各種負(fù)載。傳統(tǒng)上，中間母線電壓為48伏直流電。然而，電路板上的電子電路和器件可以使用從3.3伏到1伏的低電壓，并且具有高電流消耗。例如，最新一代處理器的核心電壓為1伏或更小，電流要求超過(guò)100 A。類(lèi)似地，其他的電子負(fù)載，如FPGA和存儲(chǔ)設(shè)備，也有嚴(yán)格的電源需求。

　　由于設(shè)計(jì)具有高效率的高降壓比DC/DC 轉(zhuǎn)換器是不簡(jiǎn)單或成本效益的，大多數(shù)設(shè)計(jì)師選擇進(jìn)一步降低總線電壓下降到24 V，12 V，或更低的使用中間總線轉(zhuǎn)換器模塊或磚。然后他們使用負(fù)載點(diǎn)（POL）高速非隔離降壓或降壓穩(wěn)壓器產(chǎn)生3.3伏的電壓低于電源不同的負(fù)載對(duì)系統(tǒng)板。

　　面臨的挑戰(zhàn)是在設(shè)計(jì)高降壓比直流/直流降壓轉(zhuǎn)換器，可提供48至3.3 V及以下，同時(shí)保持高效率和密度最低的成本。通常情況下，這種高降壓比DC / DC轉(zhuǎn)換器的效率比預(yù)想的要低，而且對(duì)設(shè)計(jì)尤其具有挑戰(zhàn)性，特別是硅器件。然而，發(fā)展的架構(gòu)與創(chuàng)新的電路設(shè)計(jì)和包裝制造商如Vicor結(jié)合已經(jīng)成功地解決了這個(gè)問(wèn)題。同時(shí)，利用氮化鎵高壓能力（GaN）設(shè)備供應(yīng)商的高效電源轉(zhuǎn)換（EPC）已經(jīng)開(kāi)發(fā)了增強(qiáng)型GaN（Egan）基于FET的Buck變換器來(lái)解決這些問(wèn)題的效率和成本有效和高功率密度。

　　用于中間總線結(jié)構(gòu)的高降壓比降壓轉(zhuǎn)換器

　　Silicon solutions

　　Let’s first look at the silicon-based solutions. One power supply maker that has been successful in developing an efficient silicon solution to address high-step-down-ratio buck converters with high density is Vicor. The company is extending its novel proprietary architecture called factorized power architecture （FPA） to generate a high-step-down-ratio DC/DC converter solution that can take 48 V bus input and step it down to load voltage as low as 1 V. Unlike traditional DC/DC circuits， Vicor’s FPA approach takes into account distribution and connector losses as well.

　　By separating the classic function of DC/DC converters， FPA and its novel power conversion building blocks， PRMs and VTMs， can provide efficient power system solutions from the intermediate bus voltage to the processor core. To accomplish this goal， FPA takes the regulation， isolation， and voltage transformation functions of a typical DC/DC converter and separates or factorizes them into individual elements. These individual components， belonging to the VI Chip family， are then arranged in the optimal power architecture as shown in Figure 1.