用于高性能分組處理的電力線濾波

　　為了確保他們的安全，許多物聯(lián)網(wǎng)（物聯(lián)網(wǎng)）應(yīng)用程序?qū)⑿枰阑饓途W(wǎng)關(guān)，以保護(hù)最敏感的設(shè)備。雖然最終節(jié)點(diǎn)將電池供電，這些防火墻將線路供電的大部分，為他們提供所需的能源運(yùn)行必要的安全檢查。這介紹了需要過濾電源線抗干擾。

　　為了應(yīng)對(duì)日益增長(zhǎng)的威脅，可以針對(duì)工業(yè)網(wǎng)絡(luò)，防火墻所使用的數(shù)據(jù)過濾系統(tǒng)變得越來(lái)越復(fù)雜。設(shè)計(jì)人員不僅部署嵌入式處理器，但現(xiàn)場(chǎng)可編程門陣列（FPGA）執(zhí)行深度包檢查任務(wù)，能夠清除可疑或惡意幀。這些先進(jìn)的設(shè)備可以有多個(gè)電源軌送入它們分別提供核心邏輯陣列和I / O單元，以及時(shí)鐘和內(nèi)存接口通道的能量。

　　Power supply coupled noise can adversely affect the phase locked loops （PLLs） used to generate reliable clock pulses， for both on-chip circuits and serial interfaces， as well as the operation of logic. Because voltages are now at 1 V or below， there is very little tolerance for changes， with the result that circuits can prove to be highly sensitive to ripple and other forms of power-supply noise.

　　Power integrity is one of the key requirements for these designs， as interruptions to processing could slow down network performance while the system recovers. As the firewalls will often be situated outside data centers where filtered power is not readily available， and may be in close proximity to industrial equipment， they will need to incorporate their own power-supply noise rejection and filtering hardware.