31 位 12MSPS 2 通道 AFE，用于 CCD/CMOS/CIS 傳感器
| Resolution (Bits) | 12 |
| Number of channels (#) | 2 |
| Samples/sec (MSPS) | 30 |
| Supply voltage (Max) | 3.6 |
| Operating temperature range (C) | -25 to 85 |
| Output data format | CMOS Parallel |
- Dual-Channel CCD Processing:
- Correlated Double Sampler (CDS)
- Sample-and-Hold Mode (S/H)
- Digital Programmable Amplifier
- CCD Offset Correction (OB Loop)
- High-Performance ADC:
- 12-Bit Resolution
- INL: ±2 LSB
- DNL: ±0.5 LSB
- No Missing Codes Ensured
- High-Speed Operation:
- Sample Rate: 31 MHz (max, Design Ensured)
- 78-dB SNR (at 0-dB Gain)
- Low-Power Consumption:
- Low Voltage: 3.0 V to 3.6 V
- Low Power: 290 mW (typ at 3.3 V)
- Standby Mode: 20 mW (typ)
- APPLICATIONS
- Copiers
- Scanners
- Facsimiles
The VSP5010 is a complete application-specific standard product (ASP) for charge-coupled device (CCD) line sensor applications such as copiers, scanners, and facsimiles. The VSP5010 provides two independent line-processing channels, and performs analog front-end (AFE) data processing and analog-to-digital conversion. Each channel features correlated double sampling (CDS) and sample-and-hold (S/H) processing stages, 14 analog-to-digital converter (ADC) blocks, a digital programmable gain amplifier (DPGA), and an optical black (OB) correction loop. Data are output in a 12-bit word; two-channel ADC data are multiplexed and then output.
The VSP5010 operates from a single 3.3-V supply. The device is available in an LQFP-64 package.
