1.概述

NXP i.MX93處理器有兩個(gè)以太網(wǎng)控制器，其中eqos是TSN網(wǎng)絡(luò)控制器。另外一個(gè)Fec以太網(wǎng)外圍設(shè)備使設(shè)備能夠在以太網(wǎng)上傳輸和接收符合IEEE 802.3-2002標(biāo)準(zhǔn)的數(shù)據(jù)，提供了一個(gè)可配置的、靈活的外設(shè)，以滿(mǎn)足各種應(yīng)用程序和客戶(hù)的需求。一般情況CPU集成MAC，PHY采用獨(dú)立芯片；CPU不集成MAC，MAC和PHY采用集成芯片。MAC和PHY工作在OSI模型的數(shù)據(jù)鏈路層和物理層。i.MX93的MAC集成在CPU內(nèi)部，所以還需要外接PHY芯片。

MYD-LMX9X開(kāi)發(fā)板外接了兩個(gè)YT8531SH千兆PHY芯片，ENET1原理圖如圖1-1：

圖1-1. ENET1原理圖

查看原理圖與《MYD-LMX9X-PinList-V1.0.pdf》得出 ENET1數(shù)據(jù)管腳與i.MX93的對(duì)應(yīng)關(guān)系如表1-2：

表1-2. ENET1引腳對(duì)應(yīng)關(guān)系

ENET2原理圖如圖1-3:

圖1-3. ENET2原理圖查看原理圖與《MYD-LMX9X-PinList-V1.0.pdf》得出 ENET2數(shù)據(jù)管腳與MYD-LMX9X的對(duì)應(yīng)關(guān)系如表1-4：

表1-4. ENET2引腳對(duì)應(yīng)關(guān)系

2.網(wǎng)卡驅(qū)動(dòng)移植2-1.查看內(nèi)核設(shè)備引腳定義在內(nèi)核中，有對(duì)i.MX93芯片的網(wǎng)口設(shè)備樹(shù)資源做了定義，此部分由芯片產(chǎn)商提供，屬于公共資源，實(shí)際上我們不需要修改這部分，只需要引用即可，如下：

PC:~/myd-lmx9x-bsp/myir-imx-linux$ cat arch/arm64/boot/dts/myir/imx93.dtsi...... fec: ethernet@42890000 { compatible = "fsl,imx93-fec", "fsl,imx8mp-fec", "fsl,imx8mq-fec"; reg = <0x42890000 0x10000>; interrupts = , , , ; clocks = <&clk IMX93_CLK_ENET1_GATE>, <&clk IMX93_CLK_ENET1_GATE>, <&clk IMX93_CLK_ENET_TIMER1>, <&clk IMX93_CLK_ENET_REF>, <&clk IMX93_CLK_ENET_REF_PHY>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, <&clk IMX93_CLK_ENET_REF>, <&clk IMX93_CLK_ENET_REF_PHY>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <100000000>, <250000000>, <50000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; status = "disabled"; };
eqos: ethernet@428a0000 { compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; reg = <0x428a0000 0x10000>; interrupts = , ; interrupt-names = "eth_wake_irq", "macirq"; clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, <&clk IMX93_CLK_ENET_QOS_GATE>, <&clk IMX93_CLK_ENET_TIMER2>, <&clk IMX93_CLK_ENET>, <&clk IMX93_CLK_ENET_QOS_GATE>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, <&clk IMX93_CLK_ENET>; assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; assigned-clock-rates = <100000000>, <250000000>; intf_mode = <&wakeupmix_gpr 0x28>; clk_csr = <0>; nvmem-cells = ; nvmem-cell-names = "mac-address"; status = "disabled"; };

上述只是對(duì)網(wǎng)口做了基本的初始化，并沒(méi)有對(duì)具體的硬件設(shè)備進(jìn)行適配，在實(shí)際的情況下需要對(duì)具體的網(wǎng)口設(shè)備進(jìn)行硬件引腳資源的適配。

2-2. 添加網(wǎng)卡設(shè)備樹(shù)節(jié)點(diǎn)根據(jù)原理圖的定義添加網(wǎng)口的設(shè)備樹(shù)配置，修改myir-imx93-11x11.dts文件，如下：

PC:~/myd-lmx9x-bsp/myir-imx-linux$ cat arch/arm64/boot/dts/myir/myir-imx93-11x11.dts......&eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rgmii-id"; phy-handle = ; status = "okay";
mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; eee-broken-1000t; }; };};
&fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; phy-mode = "rgmii-id"; phy-handle = ; fsl,magic-packet; status = "okay";
mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; clock-frequency = <5000000>;
ethphy2: ethernet-phy@2 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <6>; eee-broken-1000t; }; };};

2-3. 網(wǎng)卡設(shè)備數(shù)配置添加網(wǎng)卡設(shè)備樹(shù)節(jié)點(diǎn)的eth1_pins和eth2_pins引腳定義：

pinctrl_eqos: eqosgrp { fsl,pins = < MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e >; };
pinctrl_fec: fecgrp { fsl,pins = < MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e >; };

2-4. 配置內(nèi)核PHY驅(qū)動(dòng)位于drivers/net/phy/motorcomm.c，我們只需要把這個(gè)驅(qū)動(dòng)打開(kāi)，編譯進(jìn)內(nèi)核即可，內(nèi)核已默認(rèn)配置網(wǎng)卡驅(qū)動(dòng)，這里我們不再描述。最后編譯內(nèi)核源碼，把新生成的設(shè)備樹(shù)dtb文件更新到板子即可。

2-5. 網(wǎng)絡(luò)測(cè)試

• 測(cè)試ENET1

root@myd-lmx9x:/# ping www.baidu.com -I eth0PING www.baidu.com (14.215.177.39): 56 data bytes64 bytes from 14.215.177.39: seq=0 ttl=56 time=7.987 ms64 bytes from 14.215.177.39: seq=1 ttl=56 time=8.030 ms64 bytes from 14.215.177.39: seq=2 ttl=56 time=7.250 ms

• 測(cè)試ENET2

root@myd-lmx9x:/# ping www.baidu.com -I eth1PING www.baidu.com (14.215.177.39): 56 data bytes64 bytes from 14.215.177.39: seq=3 ttl=56 time=7.507 ms64 bytes from 14.215.177.39: seq=4 ttl=56 time=7.488 ms64 bytes from 14.215.177.39: seq=5 ttl=56 time=7.151 ms64 bytes from 14.215.177.39: seq=6 ttl=56 time=7.043 ms